1 to 25 of 87 Tcl Jobs in the UK

aware that any offer of employment is conditioned upon the successful completion of a pre-employment verification. Desired Characteristics Working knowledge in VHDL, scripts (TCL, Bash, Python), Verilog, SystemVerilog, Xilinx/Altera/Lattice FPGA/Soc development tools and ModelSim, structure of SoC processors, memory (DDR, block RAM or More ❯

prior to implementation. Key Requirements: Strong FPGA/SoC design background with RTL skills in (System) Verilog and scripting skills in languages such as TCL, Python, etc. Experience implementing designs on AMD Xilinx UltraScale devices using the Vivado tool suite. Detailed understanding of timing constraints and ability to improve designs More ❯

Test & Measurement or scientific markets. Experience with tools such as Vivado, Modelsim, Visual Studio, Git, and Jira, as well as scripting languages (Python, Perl, TCL), Clock Domain Crossing techniques, and High-Level Synthesis, will be an advantage. We are looking for a detail-oriented, creative, and organised individual who can More ❯

Test & Measurement or scientific markets. Experience with tools such as Vivado, Modelsim, Visual Studio, Git, and Jira, as well as scripting languages (Python, Perl, TCL), Clock Domain Crossing techniques, and High-Level Synthesis, will be an advantage. We are looking for a detail-oriented, creative, and organised individual who can More ❯

Test & Measurement or scientific markets. Experience with tools such as Vivado, Modelsim, Visual Studio, Git, and Jira, as well as scripting languages (Python, Perl, TCL), Clock Domain Crossing techniques, and High-Level Synthesis, will be an advantage. We are looking for a detail-oriented, creative, and organised individual who can More ❯

/CD, Artifactory. Experience with application layer protocols, such as DNP, 1588, MQTT, and more. Knowledge of electronic components and PCB reworking. Experience with TCL scripting. Equal Employment Opportunity Statement Individuals seeking employment at Camlin are considered without regard to race, colour, religion, national origin, age, sex, marital status, ancestry More ❯

verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. SystemVerilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies – UVM/OVM, formal, low power, emulation. Exposure to all stages of More ❯

verification environments. Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies - UVM/OVM, formal, low power, emulation. Exposure to all stages of More ❯

C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), and hardware verification languages e.g. SystemVerilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies – UVM, formal, low power, emulation. Exposure to all stages of verification: requirements More ❯

C/C++ based SoC verification environments. Knowledge of assembly language (preferably ARM), and hardware verification languages e.g. (SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.). Experienced in one or more of various verification methodologies – UVM, formal, low power, emulation. Exposure to all stages of verification: requirements More ❯

co-verification and multi-mode simulation . Familiarity with HW acceleration techniques like emulation . Experience with verification infrastructure automation (e.g., Perl, Python, Java, Tcl, IP-XACT, UCDB ). Strong knowledge of C programming for verification tasks. Demonstrated ability to listen to customer feedback , recognise opportunities for technical innovation , and More ❯

co-verification and multi-mode simulation . Familiarity with HW acceleration techniques like emulation . Experience with verification infrastructure automation (e.g., Perl, Python, Java, Tcl, IP-XACT, UCDB ). Strong knowledge of C programming for verification tasks. Demonstrated ability to listen to customer feedback , recognise opportunities for technical innovation , and More ❯

co-verification and multi-mode simulation . Familiarity with HW acceleration techniques like emulation . Experience with verification infrastructure automation (e.g., Perl, Python, Java, Tcl, IP-XACT, UCDB ). Strong knowledge of C programming for verification tasks. Demonstrated ability to listen to customer feedback , recognise opportunities for technical innovation , and More ❯

Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols – Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers Memory controllers PCB Layout ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits More ❯

Verilog, System Verilog Senior FPGA Engineer desirable skills High-speed protocols – Ethernet, PCIe, USB, NVMe, CXL etc C/C++. Linux, Bash, Python, VHDL, tcl Jira, Git VHDL High speed transceivers Memory controllers PCB Layout ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Position : Senior FPGA Engineer Location : WFH within reach of Portsmouth Salary : £60-95k Benefits More ❯

FPGA Engineer desirable requirements: PCI Express, Ethernet, CoaXPress, MIPI, QSFP and DDR4/5 JTAG-based test, (XJTAG ideal) C/C++, Python/TCL/Shell CI/CD Agile Position: FPGA Engineer Location: Slough Salary: £45-65k Key Skills: FPGA design Desirable skills: PCI Express, Ethernet, CoaXPress More ❯

and practical experience of working on Processor based system designs Technical team leadership, mentoring or coaching experience. Knowledge of shell programming/scripting (e.g. Tcl, Perl, Python etc.) “Nice To Have” Skills and Experience: High level programming experience such as C/C++ and/or assembly programming Experience in More ❯

Engineer desirable requirements: PCI Express, Ethernet, CoaXPress, MIPI, QSFP and DDR4/5. JTAG-based test, (XJTAG ideal). C/C++, Python/TCL/Shell CI/CD Agile ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Position : FPGA Engineer Location : Slough Salary : £45-60k Key Skills : FPGA design Desirable skills : PCI Express, Ethernet, CoaXPress More ❯

Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Principal/Lead Storage Verification Engineer Desirable skills: Experience of Formal Verification (Jasper Gold or VC More ❯

experience of: Translating design requirements into RTL Deriving functional requirements for verification SystemVerilog UVM test benches Scripting & REST APIs (e.g., Perl/Python/TCL) Team player with good verbal and written communication skills Principal/Lead Storage Verification Engineer Desirable Skills: Experience of formal verification (Jasper Gold or VC More ❯

Skills and Qualifications: Strong experience with FPGA architectures , including AMD/Xilinx and Lattice . Proficiency with FPGA development tools and scripting languages like TCL . Deep understanding of verification methodologies and simulation tools. Familiarity with interface technologies and standards, including JESD204, SMPTE, and CameraLink . Experience with algorithm development More ❯

using PCB design software (Altium). Experience developing application software for Windows, Android, Linux and LabVIEW environments. Experience with programming (C, C++, Python, Perl, Tcl). Familiarity with common communications protocols (SPI, I2C, CAN, USB, RS-232). High degree of comfort working on early phase research projects. Signal processing More ❯

knowledge of FPGA tool flows (synthesis, partitioning, place & route, timing analysis). Excellent skills in SystemVerilog/Verilog/VHDL. Scripting in Python/Tcl Driver expertise The company offer an excellent salary, along with a bonus up to 85%, flexible and hybrid working, exciting technology and a great team More ❯

Strong knowledge of FPGA tool flows (synthesis, partitioning, place & route, timing analysis) Excellent skills in SystemVerilog/Verilog/VHDL Scripting in Python/Tcl Driver expertise The company offers an excellent salary, along with a bonus up to 85%, flexible and hybrid working, exciting technology, and a great team More ❯

of ASIC/FPGA design techniques and methodologies. Hands-on RTL Design – Experience at IP or SoC level using SystemVerilog, C++, Python, Perl, or TCL . Verification Knowledge – Familiarity with UVM, formal verification, assertions, and coverage bins . Experience with GPU/CPU design – Understanding of CPU, DSP, or FPU More ❯