Verification Engineer Jobs in Avon

2 of 2 Verification Engineer Jobs in Avon

Principal Verification Engineer

Bristol, Avon, South West, United Kingdom
Hybrid / WFH Options
SJ Sourcing
Job Title: Principal Verification Engineer Location: Bristol (Hybrid working) Salary: Competitive salary based on experience Job Type: Full-time, Permanent Are you a passionate and experienced engineer with expertise in hardware verification? Are you ready to take on an exciting new challenge in the fast-paced … automotive semiconductor industry? Join an innovative team in Bristol as a Principal Verification Engineer and play a key role in shaping the future of mobility! Key Responsibilities: Develop and maintain System Verilog - UVM testbenches and take ownership of complex verification tasks. Lead the development of new SV … UVM verification components and ensure the testbench quality and performance. Debug failing test cases and provide solutions to root causes. Define and write functional coverage models to meet project targets. Contribute to verification strategies and architecture, ensuring that test benches meet sign-off targets (coverage, functional safety, and More ❯
Employment Type: Permanent, Work From Home
Posted:

Senior Staff Verification Engineer

Bristol, Avon, South West, United Kingdom
Hybrid / WFH Options
SJ Sourcing
Senior Verification Engineer Location : Bristol, UK Employment Type : Full-time, Permanent Hybrid Working Available Preferred Start Date : February 2025 Are you a passionate and experienced engineer looking to take your career to the next level? Join a leading company in the automotive semiconductor industry and become an … integral part of an innovative team focused on shaping the future of mobility. We are seeking a Senior Staff Verification Engineer to help develop and maintain cutting-edge testbenches and verification components. In this critical role, you will be responsible for developing System Verilog - UVM testbenches , solving … complex problems, and contributing to the strategy and architecture of IP verification . Key Responsibilities: Develop and maintain System Verilog - UVM testbenches for complex verification tasks. Lead the development of new SV UVM verification components . Understand and modify Specman-e testbenches as needed. Debug failing test More ❯
Employment Type: Permanent, Work From Home
Posted: